14.31818 MHz

Every computer keeps time by counting ticks of a hardware timer, and each timer runs at some fixed frequency. Look those frequencies up and one thing stands out: they are not round numbers. The HPETHPET ticks at 14.31818 MHz; the ACPI PMACPI PM timer, at 3.579545 MHz. Nothing about a modern chip explains digits like these: no design target, no unit conversion, no power of two.

The two are at least related: 14.31818 is exactly four times 3.579545, so they share an origin. That origin has nothing to do with computers. The digits were fixed in 1953 by a committee designing color television, and every PC since has carried them forward untouched — fossils of a decision that predates the personal computer.

From a TV standard to 3.579545 MHz

The origin traces to the National Television System Committee (NTSC), which began work on a color standard in 1950 and had it approved in 1953. The hard constraint was backward compatibility: a color broadcast had to stay watchable on the millions of black-and-white sets already in living rooms. The standard solves this with luminance–chrominance encoding. The picture splits into a luminance signal (the old monochrome brightness, which B&W receivers already decode) and a chrominance signal (a single subcarrier carrying two quadrature I/Q color components).

The design reduces to a single question: at what frequency $f_c$ should the chrominance signal (the color subcarrier) sit so that it disturbs a black-and-white picture as little as possible? Four constraints determine it.

Condition 1 — Bandwidth. $f_c$ should be as high as possible; a higher subcarrier produces a finer, less visible noise structure. The ceiling comes from the video bandwidth. The American standard caps the maximum video frequency at $f_{max}=$4.18 MHz, and experiments showed the gap $f_{max}-f_c$ must stay above 0.6 MHz, or the image visibly distorts:

$$ f_{max}-f_c \geq 0.6~\textrm{MHz} $$

That fixes the upper bound:

$$f_c \leq 3.58~\textrm{MHz}.$$

Condition 2 — Line frequency. To hide the subcarrier on a B&W screen, $f_c$ must be an odd half-integer multiple of the horizontal line rate $f_h$:

$$f_c=(2n+1)\frac{f_h}{2}.$$

With an odd multiplier, the chrominance peaks fall between the luminance peaks from one line to the next, so the interference averages out visually. An even multiplier 2n aligns the peaks instead, creating a strong pattern of vertical bars.

Condition 3 — Audio spacing. The same averaging principle must also keep the subcarrier clear of the sound carrier. So the distance between the sound-carrier spacing $f_{\Delta s}$ and $f_c$ must again be an odd half-integer multiple of $f_h$:

$$f_{\Delta s}-f_c=(2m+1)\frac{f_h}{2}.$$

Substituting $f_c=(2n+1)f_h/2$:

$$f_{\Delta s}=(2m+1)\frac{f_h}{2}+(2n+1)\frac{f_h}{2},$$

so the sound spacing has to be an integer number of line rates:

$$\frac{f_{\Delta s}}{f_h}=m+n+1=k.$$

At this point the existing black-and-white parameters constrain the result. The B&W standard had already fixed a 30 Hz frame rate at 525 lines (15750 lines per second, a value dictated by the vacuum-tube technology of the day), so $f_h=$15750 Hz, and it had fixed the sound spacing at exactly $f_{\Delta s}=$4.5 MHz. Together they give

$$\frac{f_{\Delta s}}{f_h}=\frac{4.5~\textrm{MHz}}{15750~\textrm{Hz}}\approx285.714285714,$$

which is not an integer. The nearest one is 286. The audio carrier can’t move (legacy receivers would lose the sound), but the line rate can, so the standard redefined $f_h$ to make the ratio exact:

$$f_h=\frac{f_{\Delta s}}{286}=15734.26573~\textrm{Hz}.$$

The shift is tiny, a factor of 15750/15734.26573 $\approx$ 1.001, but it is the reason NTSC video runs at 29.97 Hz per frame and 59.94 Hz per field instead of a clean 30/60.¹

Condition 4 — Buildable oscillator. A practical subcarrier also has to be inexpensive to synthesize with frequency-divider chains, which works best when the odd multiplier (2n+1) factors into small primes. Combining the bound from Condition 1 with the new line rate:

$$ 2n+1 = \frac{2f_c}{f_h} \leq \frac{2\cdot 3580000~\textrm{Hz}}{15734.26573~\textrm{Hz}} \approx 455.0578 $$

Since $f_c$ should be as large as possible and (2n+1) must be an odd integer, the largest usable value is 455, and it factors into small primes well suited to a divider chain:

$$(2n+1)=5 \cdot 7 \cdot 13=455.$$

The number. The four constraints leave a single answer, the NTSC colorburst frequency:

$$f_c=(2n+1)\frac{f_h}{2}=455\cdot\frac{15734.26573~\textrm{Hz}}{2}\approx 3.579545~\textrm{MHz}.$$

This value is the source of 3.579545 MHz. For the full television side of the account, see Analog TV Broadcast SystemsAnalog TV Broadcast Systems and Measuring Differential Gain and Phase
By Randy StephensMeasuring Differential Gain and Phase.

From 3.579545 to 14.31818 MHz

The step from a broadcast standard to a CPU clock runs through one of the first PC clock generators: the Intel 8284. The 8284 supplied the clock for the Intel 8086/8088. The 8088 was rated for 5 MHz, and its clock needed a 33.3% duty cycle (high 1/3 of the time, low 2/3), which is easiest to produce by dividing a source about three times higher (near 15 MHz) by three.

At the time, home machines often used a television set as the display, so the Color Graphics Adapter (CGA) had to generate the NTSC subcarrier itself. A 3.579545 MHz signal was therefore already present on the board.

Adding a second crystal just for the CPU was expensive, so the design reused the one already present for CGA. A single master oscillator at 14.31818 MHz (four times the NTSC subcarrier) drives both: divide by 4 for the 3.579545 MHz CGA color clock, divide by 3 for the 4.77272666 MHz CPU clock. That left the CPU about 4.5% below its 5 MHz limit — a deliberate trade of a little speed for one fewer crystal, and cheaper chips. Tim Paterson, the original author of MS-DOS, tells this story in IBM PC Design Antics
By Tim PatersonIBM PC Design Antics, and Calvin Hsia retells it in Why was the original IBM PC 4.77 Megahertz?
By Calvin HsiaWhy was the original IBM PC 4.77 Megahertz?. Satish K. Karna’s Microprocessors—GATE, PSUs and ES Examination and B. Govindarajalu’s IBM PC and Clones: Hardware, Troubleshooting and Maintenance cover the 8284 in more detail.

The value then spread through later hardware. ACPI PMACPI PM reuses the 3.579545 MHz NTSC frequency because the hardware to produce it was already present. HPETHPET needs at least 10 MHz, and rather than add another oscillator, it reuses the 14.31818 MHz master clock. The PIT (Programmable Interval Timer, the Intel 8253/8254) takes that same master clock divided by 12, giving 1.193182 MHz. Every clock on the board is a simple division of the one 14.31818 MHz master:

Consumer	Divisor	Frequency
CGA color subcarrier	÷ 4	3.579545 MHz
CPU (8088)	÷ 3	4.77272666 MHz
PIT (8253/8254)	÷ 12	1.193182 MHz

Because they share a source, the timers stay in exact integer lockstep: CGA Frequency = 3 × PIT Frequency and CPU Frequency = 4 × PIT Frequency.

The 3.579545 MHz colorburst crystal was eventually produced in such volume that it became one of the cheapest quartz crystals on the market, and it went on to serve as a general-purpose timing reference well beyond television. The odd digits in a modern timer’s frequency are therefore not arbitrary. They are the 1953 color-TV subcarrier, multiplied by four and carried forward through decades of backward compatibility.

Adapted from the “History of Magic Numbers” section (Chapter 9, “Hardware Timers”) of my book Pro .NET Benchmarking.